DLL is the digital format of PLL, used to insert a delay in the clock signal to the desired value in accordance with the circuit it is included in the design. In usual emphasis, the clock timing properties are delayed, thereby increasing the output produced to an expected level and thus controlled. DLLs are also utilized for clock and data recovery (CDR) systems. To elaborate the functioning of a DLL utilized as a functional block, a negative delay gate is used with the clock reference input signal. It is a kind of PLL circuit only with the difference of the usage of a delay element in place of an oscillator circuit. The internal component of the DLL circuit contains a phase locator (PD) which compares the phase of the reference clock and feedback clock phase. Depending on the UP or DOWN signal of the reference clock, signal charge pump either charges upward or downward. They are shown in Figure 14.3. The charge pump output is filtered out through a low pass filter finally at the far end received by the delay line. Hence, with the phase locator circuitry input, the delay line gets delays in the output clock frequency to the phase locator. The delay line comprises cascaded connections of specific delay gates or combinational elements. The delay gates are in the form gates like inverters, NAND gate or the XOR gate.
Another methodology in which the DLL functions is that DLL is applied to the input of the clock which is synchronized with positive (+ve) or negative (–ve) delay. Each unit of the delay in the chain contains a combinatorial multiplexer. The multiplexer control input is kept on updating with another control circuit which generates the (–ve) negative delay effect. Hence, the output of the DLL is positively or negatively delayed clock pulse.
The DLL finds its application in the locking of the clock input with voltage-controlled delay line (VCDL) or digitally controlled delay line (DCDL). The clock signal can be locked up to 1 or 1/2 of the clock cycle when the subtlety increases the duration of lock and it falls behind (Kazemier et al. 2017; Casto 2018).
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