Conclusion

In this work, we have briefed the clock generation circuit as PLL and DLL. These circuits generate a new clock that can be used as a reference edge in complex devices. Other internal components of the decision are synchronized to the active edge. Mean data transfer is possible on the active edge else the same value of data is to be held. A stable clock is the most important signal of the design. Depending on the application, fine and coarse resolutions are required which overcorrect themself. An important feature of a clock signal is included in the second section. The clock is attributed as skew, slew, jitter, etc. which arises due to path delay and interconnect delay in the critical path. Electronic design automation (EDA) tool uses the statistical table to calculate delay as a function of capacitance and input transition. Wire and interconnection delays are caused by the RC delay model with charging and discharging nature of the capacitor. The selection of PLL, DLL and internal component in the path is based on the application.