Buffer-​based delay line

A buffer comprises NMOS and a PMOS with the placement of cells in the opposite direction of CMOS inverter. NMOS is kept on the top and PMOS on the bottom, both being the connection of V_DD and GND not altered. Here NMOS is connected to V_DD, and PMOS is connected to ground. The structure was made such that they only pass the voltage as a buffering unit and do not change the signal. The critical feature of the DLL is that no filtering procedure is required for the input jitter present in the clock path due to noise and unavoidable delay elements. Limitation of DLL is the presence of clock, however, unlike in the PLL, the jitter does not accumulate over the cycles or increase further, it just continues to possess the intrinsic values. The frequency of DLL with application input and output remains the same, whereas the input and output are in delayed format of each other. Due to this, there is no phase error that might get submerged. There are various sources of noise found in DLL circuit like the delay line nervousness to the supply, the device crosstalk and the clock buffers. Hence, a DLL must be designed to have a low jitter input.