Inverter-based VCDL device design was started with a schematic design using “Cadence Virtuoso” schematic composer using CMOS 90-nm technology, and simulation result was obtained with cadence spectre simulator. The inverter-based and the buffer-based delay lines work in the following manner: When an input voltage is supplied as the reference edge of the clock to the first input terminal of the inverter or the buffer, the input voltage passes through all of the transistors after experiencing some propagation delay and gets transmitted on to the next inverter stage. There can be many inverter stages. The amount of delay achieved increases with the number of stages. The uses as the basis the thesis work employing a five-stage inverter-based delay line which was made using the Cadence tool. To increase the delay in the delay line, we need to exploit the RC delay offered in the circuit. To accomplish this in practical designs, a cascaded stage of other devices is applied in connection to the main delay line. These devices are called delay elements. Examples of these delay elements include NAND gates, 3T XOR gates.
Leave a Reply