Delay measurement

During research to understand the delay calculation, an inverter-​based delay is the starting point. In the inverter-​based delay lines, a minimum delay in the transition of the output from the input is offered. However, delay of the circuit is not only due to delay of inverter gates but also includes the delay offered by interconnection and wires during the transmission of the input to the output. The inverter-​ and the buffer-​based delay lines work in the following manner:

When an input voltage is supplied as the clock signal for reference to the first input of the inverter or the buffer, the input voltage passes through all of the transistors after experiencing some propagation delay and gets transmitted on to the next inverter stage. There can be many inverter stages. The amount of delay achieved increases with the number of stages. To increase the delay of the delay line, we need to exploit the RC delay offered in the circuit. To accomplish this in many designs, a cascaded stage of other devices is applied in connection to the main delay line. These devices are called delay elements. The transfer feature of a NOT gate is shown. Input–​output signals show variation in the rising and falling curve from the ideal threshold owing to the delay of the inverter circuit shown in Figure 14.2. The propagation delay is divided into two sections: τ_PHL and τ_PLH. These delays are calculated separately while measuring the delay between the input and output during transitions.

The time taken for the delayed transition between the midway of the rising input and midway of the falling output is given by τ_PHL.

The time taken for the delayed transition between the midway the falling input and midway of rising output is given by τ_PLH.

The critical assumption made to achieve the previously given switching characteristics of an MOS inverter is that the rise and fall times are zero for each step pulse.

The voltage at V_50% actually is given asV50%=VOL+12(VOH−VOL)andV50%=12(VOH+VOL).

Also, from the graph we can evaluate thatτPHL=t1−t0 andτPLH=t3−t2

Hence, the average value of propagation delay in terms of τ_PHL and τ_PLH is given asτP=τPHL+τPLH2.

For the calculation of the values of the delay times, τ_PHL and τ_PLH, we use the estimate of the charging and discharging average capacitance current. For the capacitance current during a transition being equivalent to I_avg, delay times can be represented asτPHL=CLOADΔVHLIavg,HL=CLOAD(VOH−V50)Iavg,HLandτPLH=CLOADΔVLHIavg,LH=CLOAD(V50−VOL)Iavg,LH.

Average current while the high to low switching is given as a term dependent upon the current from start to end of a transition period isIavg,HL=12[iC(Vin=VOH,Vout=VOH)+iC(Vin=VOH,Vout=V50)].

Similarly,Iavg,LH=12[iC(Vin=VOL,Vout=V50)+iC(Vin=VOL,Vout=VOL)].

The approach using the average current does not prove to be an efficient method as it ignores the various aspects of current due to capacitance that are present between the input and the output transition. For more accurate results, we solve the state equation for output node in the time domain analysis. This can be achieved by measuring the differential voltage connected with the output terminal which is given below:CLOADdVoutdt=iC=iD,p−iD,n.

During the conduction period of the NMOS, the initial operation is in the saturation region. However, for the output voltage below (V_DD – ​V_{T, n}), the NMOS enters the linear region.

Considering the NMOS to be in the saturation region first, we getiD,n=kn2(VOH−VT,n)2.

The saturation region is independent of the output voltage; so, we can approximate the load current as∫∫t=t0t=t1’dt= −2CLOADkn(VOH−VT,n)2∫VOUT=VOHVOUT=VOH−VT,ndVOUT.

Solving for the time range t1′ to t₀, we gett1’−t0=2CLOADVT,nkn(VOH−VT,n)2.

For the NMOS in the linear region,iD,n=kn2[2(VOH−VT,n)VOUT−VOUT2].

Solving between the time interval t1′ and t₁∫t=t1’t=t1dt=−2CLOAD∫VOUT=VOH−VT,nVOUT=V50(1kn[2(VOH−VT,n)VOUT−VOUT2])dVOUT.

Simplifying, we gett1′−t0=2CLoadkn12(VOH−VT,n)ln(2(VOH−VT,n)−V50%V50%).

The final propagation delay times are found by combining Equations (14.1) and (14.2), thereforeτPHL=CLOADkn(VOH−VT,n)[2VT,nVOH−VT,n+ln(4(VOH−VT,n)VOH+VOL−1)].

For V_OH = V_DD and V_OL = 0,τPHL=CLOADkn(VDD−VT,n)[2VT,nVDD−VT,n+ln(4(VDD−VT,n)VDD−1)].(14.1)

Similarly, for the charge down event of the capacitance, τ_PLH can be found asτPLH=CLOADkP(VOH−VOL−|VT,P|)[2VT,pVOH−VOL−|VT,P|+ln(2(VOH−VOL−|VT,P|)VOH−V50−1)].

For V_OH and V_OL = 0,τPLH=CLOADkP(VDD−|VT,P|)[2VT,pVDD−|VT,P|+ln(2(VDD−|VT,P|)VDD−1)].(14.2)