What is clock signal?

A clock signal is the reference signal used to compare as a reference in circuits for synchronization of input and output signals. The clock signal has a definite period, and half of the period is known as pulse width which changes its value from high to low or low to high (Jovanović et al. 2003). Clock signals are used as the reference or pulse signals in most of the electronic systems today. Many of us generally regard the clock signals as only control signals. However, the following attributes make the clock signals significant (Earl McCune 1994):

1. They possess the greatest fan-​out.
2. They travel enormous distances in any circuit.
3. They typically operate at the highest speed possessed in the circuit concerning both control and data signals.

Since the clock signals provide temporal reference for both control and data signals, they must be immaculate, sharp and precise. They should possess high resolution with proper synchronization. On the other hand, the absence of a clock signal can severely limit the operation of the circuit on the whole and even cause catastrophic errors.

The most desirable factor in the excellent performance of digital circuits and mixed-​signal VLSI circuits is the synchronization of the system to be able to tackle the very high speed flow of data with fine resolution. With the help of delay in the signals, we can increase not only the time resolution but also the precision that a particular digital signal holds. This is a vital quality in high-​tech systems nowadays. Several emerging applications require fine time resolution. Due to the needs like excellent time resolution, clock synchronization and frequency monitoring, we require the delay in the circuits which can be easily achieved with the help of phase-​locked loops (PLL) and delay locked loops (DLL) (Johnson et al. 1992; Woo 1993).

The areas that require excellent time resolution are (Deanger 1998; Morales 1990; Bult and Wallinga 1988):

1. High-​speed communication
2. Military-​related security applications
3. Testing and measurement purposes
4. Health-​related instruments
5. Accurate control system
6. Agriculture management system

Military and biomedical applications: All the applications like military code encoding and decoding, biomedical sensors as well as patient monitoring systems (PMS) require high precision with high resolution. Hence, the clock generation circuitry in these circuits employs a DLL/PLL with efficient use of delay lines to provide the desirable synchronization. The data sampling rate of these devices is kept faster than the maximum data rate. Thus, they can have the abiqlity to control data timing with precision.

A fine, precise application device requires a clock signal interval as small as 25–​600 ps. The clock edge would be lower than the least width by an order multiplying factor. The time reference in the digital devices is responsible for the synchronization of correct arrival of the clock edge and the rate of flow of data on the different clock edge. A few famous examples of digitally synchronized systems are logic analyzers, pulse data generators as shown in Figure 14.1. For this purpose, the synchronization, precision and resolution of the clock signal are of utmost importance. Therefore, the clock signal generation circuitry generally comprises additional elements like buffers and PLL/DLL. PLL and DLL use a variable quality: PLL is based on phase frequency and DLL is based on variable delay generated by the controlled delay line. This aims to develop programmable delay lines which can easily be configured to achieve the maximum delay. This will be accomplished by adding different kinds of delay units to the fixed delay lines or designing delay lines based upon the usage of different sequential and combinational logic elements.

The clock signal is majorly classified in four categories:

1. Synchronous clock: Each unit of the circuit works on the same frequency. This is the clock frequency generated by oscillator as given to all groups in the design.
2. Asynchronous clock: Each unit in the model receives a different clock; the output of one unit is utilized as a clock reference for the following group. The asynchronous signal can be used for handshake signals for communication and microcontroller.
3. Mesochronous clock: Here, every group is given the same clock frequency, but the phase of the clock is not defined. Recover decides the phase of the aforementioned kinds of signals and a unique technique is required from the data being transmitted.
4. Plesiochronous clock: In this type of clocking strategy frequency at each unit is almost the same, but the phase of the clock is not the same. For every unit, the phase keeps on drifting at a slower speed. Hence, they need too a technique to identify when the active edge of the clock is available on the output drifted from the input by more than half. Delay in the electronic design is defined as the retardation that the signal faces when traveling from source input to destination (Santos et al. 1995; Dehng et al. 2000; Cheng and Lo 2007).

Different kinds of delays found within the circuit:

1. Propagation delay: It is defined as the time required by the signal to flow from the input terminal to the output terminal of a logic gate. Most frequently it is defined as a rising–​falling waveform applied to a block; maximum time is taken from rising input/rising 50% mark to the output rising/falling 50% mark.
2. Gate delay: The maximum time required by a logic gate to compute the expected output. Time taken on receiving an input for generating the expected output is termed as gate delay. For nanometer design, its values are in the unit of nanoseconds with precision picoseconds.
3. Contamination delay: It is the minimum time required from the input 50% threshold to the output 50% threshold. Contamination delay follows the minimum delay along the circuit, that is, it provides the shortest path.
4. Transmission delay: It is the delay that arises due to the data being transmitted which is not dependent on the input or output nodes.

Propagation delay affects most of the circuits and it is by far the largest contributor of all the other delay kinds. Due to delays, the overall speed, performance and effectiveness of the device under test are hampered or sometimes it gives the wrong result. There are various designs in which the paths do not require much effort for having the more precise observations of the speed. However, there are critical paths in the circuit which refer to the longest path in terms of delay. Delay associated with the critical path is known as total delay of the circuit (Kumar et al. 2011). Critical paths cannot alter the performance of the overall system and these paths require special monitoring in accordance to the timing details (Singh et al. 2012). There are four levels with respect to which the critical paths can be distributed, namely (i) algorithm level, (ii) cell level, (iii) transistor level, (iv) floorplan/layout level.

Standard results are acquired at architecture level. The critical paths are the necessary for determination of total delay that a large circuit will possess. The shortest critical path equalizes the delay exhibited at the output. To reduce the delay, different delay models are incorporated in electron design automation tools at the design level or technology level. The most accessible and effective delay model to compute interconnection and gate delay is RC model. The RC delay model roughly follows the nonlinear transistor C–​V and I–​V curves with the average value of resistance and capacitance calculated through interpolation and statistical analysis over the switching speed of the gate. This estimation is very effective for delay measurement. Similarly, delay offered through pin capacitance wire and their interconnection is measured using a nonlinear delay model: Elmore delay model and T and Pi RC delay model.